The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A Delay-Locked Loop (DLL) is a circuit that produces an output signal having a specified phase relationship with an input signal. For example, the DLL may be used to produce the output signal having a transition occurring at a delay from a transition of the input signal equal to a quarter, a half, or three-quarters of a clock period of the input signal. The input signal can be a clock signal.
The DLL includes one or more variable delay line circuits that are used to generate the output signal by delaying the input signal. The delay produced by the one or more delay line circuits is controlled according to a phase detect signal produced by a phase detect circuit.
The DLL also includes a lock detect circuit that produces a lock signal. The lock signal has a first value when the phase relationship of the output signal to the input signal is within an error margin of the specified phase relationship, and a second value otherwise. The DLL is considered locked when the lock signal has the first value, and unlocked when the lock signal has the second value. A circuit may use the lock signal to determine whether to perform an operation that uses the output signal, for example, receiving or sending data using the output signal as a strobe signal.